India’s push to manufacture chips locally could give electronic design automation (EDA) companies a new source of growth, as more Indian chip designs move towards commercial tape-outs.
One beneficiary could be California-based EDA company Cadence Design Systems, which expects Tata Electronics’ planned semiconductor fab in Dholera to boost chip-design activity in India.
“As the rhythm of tape-outs accelerates, the total number of design starts increases. Our business directly tracks design starts. As design starts rise in a geography, our business grows. When the Tata fab comes online in 2028, we expect to see growth driven by that increased activity,” Jayashankar Narayanankutty, group director at Cadence Design Systems in India, told Mint.
Fabless startups today often send their designs to overseas foundries for tape-outs and manufacturing; a domestic foundry would give them the option to do so in India. A tape-out is when a ’s final, verified design is sent to a foundry for initial samples before manufacturing.
The Tata fab is expected to start operations by 2028, minister Ashwini Vaishnaw said in March. In January, he had said the plant would provide fabrication support to chip startups for design tape-outs.
The opportunity comes as India’s chip-design ecosystem expands. Market research firm Mobility Foresights expects the country’s EDA tools market to grow from $3.45 billion in 2025 to $7.82 billion by 2031, driven by demand for advanced semiconductor design, particularly in artificial intelligence (AI) accelerators, autonomous vehicles and 5G chipsets.
In 2025, Cadence’s global revenue rose 14% to $5.3 billion, while net profit increased 5.1% to $1.1 billion. The company follows a January-December financial year.
“Having a local commercial fab reduces entry barriers for Indian companies to engage directly with a foundry and get silicon manufactured locally. It improves scheduling and slot access. Today, global foundry process lines are heavily congested, requiring long wait times to secure manufacturing slots, especially on advanced nodes,” Narayanankutty said.
Paid demand
For Cadence, the opportunity is tied to the growing number of startups progressing towards commercial chip development. use EDA software to design, verify and prepare chips for manufacturing, while semiconductor foundries work with them to enable and optimize process design kits (PDKs), which contain the technology files, design rules, models and libraries needed for a particular manufacturing process.
EDA tools can be expensive for startups. Under the government’s design-linked incentive (DLI) and Chips to Startup programme, companies including Synopsys, Cadence, IBM, and Siemens EDA provide access to such tools through a shared pool.
“In the DLI (design-linked incentive) programme, (EDA tools) licenses are shared across multiple startups from a central pool, which sometimes requires waiting for an available license slot. When a startup approaches commercial tape-out, they cannot afford delays, so they purchase dedicated licenses directly from us, to run on their own servers or on our cloud,” Narayanankutty said.
Narayanankutty said that while 24 startups received direct financial support from the government under the DLI 1.0 scheme, Cadence has supported 106 startups with their chip designs. Of these, more than 80 are at advanced stages of product development.
More than 20%, or 15–18, of those 80 companies have made direct commercial software investments with Cadence as they raised external venture capital funding, he said.
Peak XV-backed chip-design startup Mindgrove said EDA tools are priced for large, funded companies, making costs steep for young startups.
“Across the full budget for building a chip, covering design, testing, IP, manufacturing, and packaging, EDA tools usually take up around 10% to 40%. The relationship is actually inverse – more complex the chip, IP and manpower dominate. EDA doesn’t rise nearly as fast,” said Shashwath TR, co-founder and CEO of Mindgrove Technologies.
According to Narayanankutty, deep-tech companies globally typically allocate 11% of revenue to R&D, with about 25% of that budget going to design infrastructure such as EDA software, intellectual property and compute hardware.
Shashwath expects India to account for a growing share of the EDA market, though the revenue impact could take time.
“In the next few years, we should be seeing more and more share of the EDA market coming from India. It may take another 3-5 years for that demand to actually show up on books as we and our peers mature,” he said.
Policy push
The Centre is also expanding support for the semiconductor ecosystem. Last month, it notified the ₹1.28 trillion semiconductor scheme 2.0, broadening its scope to include the country’s first display-chip plant, specialized compound semiconductors and critical raw materials.
Under the new DLI scheme, startups will receive grants of up to ₹15 crore as early-stage seed capital. The Centre will also offer equity-based funds to chip startups that raise private-equity funding rounds, matching funds raised from private investors.
As India explores advanced chip nodes such as sub-28nm down to 7nm, 3nm and 2nm, Cadence said it is looking to contribute as both a software provider and technology consultant.
For the ecosystem to become self-sustaining, Narayanankutty said the government or an industry consortium needs to aggregate national prototype demand. This would help secure volume pricing, guaranteed slot scheduling and lower prototype tape-out costs for Indian startups.